Known integrated circuits may be provided with a plurality of masters which are configured to issue transaction requests. These transaction requests are then sent to a respective slave configured to provide responses to the respective requests. Some protocols require that a given master receive respective responses in the same order as the requests were issued.
Associative approaches using a content addressable memory have been proposed, but such approaches may be complex and take up a significant amount of silicon. These approaches may introduce a frequency limitation which can adversely affect the performance.